The present invention relates in general to semiconductor technology and, more particularly, to structures and methods for forming inter-electrode dielectrics (IEDs) and other dielectric regions in shielded and non-shielded trench field effect transistors (FETs).
Shielded gate trench FETs are advantageous over conventional FETs in that the shield electrode reduces the gate-drain capacitance (Cgd) and improves the breakdown voltage of the transistor without sacrificing on-resistance. Conventional shielded gate trench FETs include a shield electrode below a gate electrode. The shield and gate electrodes are insulated from each other by a dielectric layer referred to as an inter-electrode dielectric or IED. The gate electrode is insulated from its adjacent body regions by a gate dielectric. Conventional methods for forming the IED and gate dielectric include thermal oxidation and oxide or nitride chemical vapor deposition (CVD) processes.
The quality, thickness, and method used to fabricate the IED are important as the IED has significant impact on electrical characteristics of the device, such as RDSon, Qgd, and Igss. The IED must be of sufficient quality and thickness to support the required voltage between the shield and gate electrodes. If the IED is too thin, shorts may occur. If the IED is too thick, it may be difficult to ensure that the gate electrode extends below the bottom surface of the body region. If these two regions are misaligned Qgd will decrease and RDSon will increase. Additionally, the gate dielectric must have low interface charges and dielectric trap charges to reduce leakage and increase dielectric quality.
Thus, there is a need for structures and methods for forming shielded gate trench FETs with improved IED and gate dielectrics.